This invention relates to timing in electronic systems, and, more particularly, to systems employing redundant, synchronous clock distribution.
The need to generate a local signal which is synchronized with an external reference signal is critical in many electronics applications such as frequency synthesis, clock recovery, clock generation and frequency demodulation. This coherence between the reference signal and the local replica is referred to as xe2x80x9cphase synchronizationxe2x80x9d. This implies either that local signal is typically either in phase with the external reference signal or is offset from the reference signal by some phase constant.
At the heart of many such synchronization circuits is some form of a phase locked loop (PLL). Phase-locked loops are feedback control loops, whose controlled parameter is the phase of a locally generated replica of an incoming reference signal. Phase-locked loops have three basic components: a phase detector, a loop filter, and a voltage-controlled oscillator.
Generally speaking, electronic systems such as computer systems produce a master clocking signal from a crystal. The master clocking signal may be fed into a PLL to produce many identical clock signals (e.g. fanout) that are used to synchronize the components of the computer system.
The master clock signal is a critical component of the computer system. The failure of the master clock signal may disable the entire system. Thus, to alleviate this problem, some systems incorporate two master clock signals, one of which is redundant. Upon a failure of the first master clock signal, the system is shut down and may be reinitialized using the second master clock signal. However, such a requirement disrupts system operation. Accordingly, it would be desirable to provide a system that can fail-over from one clock source to another clock source without causing a disruption to system operations.
The problems outlined above are in large part solved by a system and method for providing redundant, synchronized clocks in a computer system. Upon a failure of a master clock signal, the system switches over to a slave clock signal synchronized with the master clock signal. In one embodiment, switching logic is coupled to receive a first clock signal and a second clock signal. The switching logic is configured to select either the first clock signal or the second clock signal as a local clock signal. The switching logic is further configured to monitor the first clock signal for a failure. If a failure of the first clock signal is monitored, the switching logic is further configured to accept the second clock signal as the local clock signal in place of the first clock signal. The system also includes one or more clock local loads that operate according to the local clock signal. In another embodiment, the switching logic controls the input to a phase lock loop that provides the local clock signal to the local clock loads. This configuration may advantageously allow a redundant, synchronous slave clock to replace a master clock upon failure of the master clock.
In a further embodiment, the first clock source is incorporated on a first clock board, and the second clock source is incorporated on a second clock board. The system further includes, in this embodiment, a system board, and a system controller. The system board. is coupled to receive both the first clock signal and the second clock signal. The system board is configured to selectively use either the first clock signal or the second clock signal as a local clock signal. The system controller is coupled to the first clock board, the second clock board, and the system board. The system controller is configured to monitor both the first clock signal and the second clock signal for a failure. The first clock board may be removed from the system, such as upon a failure, and a third clock board placed in the system in place of the first clock board. The second clock board is switched from being the slave clock source to the master clock source. The third clock board is configured to operate as the slave clock source upon being placed in the system. The removable clock board may advantageously result in higher uptime for the system as a failed clock board may be replaced while the system is in use.
A method is likewise contemplated for providing redundant, synchronous clock signals. The method comprises, in one embodiment, a first clock source providing a first clock signal as a master clock signal to a phase locked loop (PLL). A second clock source provides a second clock signal as a slave clock signal to the PLL, where the slave clock signal is synchronized with the master clock signal. The PLL synchronizes an output clock signal with the master clock signal. The output clock signal is used by at least one local clock load for timing. The switching logic monitors the master clock signal and the slave clock signal for a failure. Upon a failure of either the master clock signal or the slave clock signal, the switching logic notifies a system controller of the failure. Upon the failure of the first clock signal, the switching logic switches the second clock signal in place of the first clock signal as the master clock signal for the PLL. Also upon receiving notice of the failure of the first clock signal, the system controller causes the second clock signal to fail-over and to take over as the master clock source to the PLL. Upon receiving notice of the failure of the first clock signal, the system controller further causes the second clock source to provide a reference control signal to the second clock source. The method may advantageously maintain continuous operation of the computer system while switching between clock sources.
In preferred embodiments, clock switching from a failed master clock to a redundant slave clock is automatic and does not interrupt or interfere with the operations of the computer system. No halt and restart are necessary. The clock change is transparent to the local clock loads using the local clock signal.